In this episode, Andy Turudic talks with Georgia Tech’s Professor Shaolam Li about their ECE department’s new analog IC design course where close to a dozen teams of three undergrad and one graduate student are fully hands-on designing real silicon, from schematic through tapeout, with resumption of the course to perform functional verification in a returning semester, after fabrication on a 300mm wafer by Texas Instruments.

Making logic chips has never been an easy task, and it is one that has been further challenged by advances in scaling as well as advanced topologies like chiplets. From the race to 2nm-foundry creation for next-generation wafer development and the related issues of packaging, engineers must develop new solutions. In this episode, we talk to Henri Richard, GM and president of Rapidus Design Solutions, about the state of the art and the solutions his company is developing.

The growth in high-performance computing and AI in advanced chip architectures is creating issues when it comes to intra-chip data management, especially as they migrate to chiplet-based topologies. Addressing this chip-level issue, Avicena announced its scalable LightBundle chiplet interconnect solution, offering ultra-high density die-to-die connections with a multi-Tbps/mm shoreline bandwidth density at sub-pJ/bit energy efficiency. In this podcast we talk to Bardia Pezeshki, Founder and CEO of Avicena, about the issues of intra-chip data management and his company’s solution.